DRAM, FLASH, and SRAM are the three major conventional semiconductor memories on the market. The manufacturing cost of DRAM is the lowest. However, in addition to shortcomings such as the need for refreshment, relatively low speed and high power consumption, DRAM is volatile. Consequently, a DRAM loses data when the power is turned off. FLASH memory is non-volatility, but is very slow. The write cycle endurance for a FLASH memory is less than one million cycles. This write cycle endurance limits the application of FLASH memories in some high data rate market. SRAM is a fast memory. However, SRAM is volatile and takes too much silicon area per cell. In search of a universal random access memory that offers high speed, non-volatility, small cell area, and good endurance, many companies are developing thin film Magnetic Random Access Memories (MRAM).
Conventional MRAMs can be fabricated with a memory cells using a variety of magnetic elements, such as an Anisotropic Magnetoresistance (AMR) element, a Giant Magnetoresistance (GMR) element, and a Magnetic Tunneling Junction (MTJ) stack. For example, a conventional MTJ stack is relatively simple to manufacture and use. Consequently, an MRAM is used as the primary example herein.
The magnetic field for changing the orientation of the changeable magnetic vector is usually supplied by two conductive lines that are substantially orthogonal to each other. When electrical current passes through the two conductive lines at the same time, two magnetic fields associated with the current in the two conductive lines act on the changeable magnetic vector to orient its direction.
FIG. 1A depicts a portion of a conventional MRAM 1. The conventional MRAM includes conventional orthogonal conductive lines 10 and 12, conventional magnetic storage cell having a MTJ 30 and conventional transistor 13. In some designs, the conventional transistor 13 is replaced by a diode, or completely omitted, with the conventional MTJ cell 30 in direct contact with the conventional word line 10. The conventional MRAM 1 utilizes a conventional magnetic tunneling junction (MTJ) stack 30 as a memory cell. Use of a conventional MTJ stack 30 makes it possible to design an MRAM cell with high integration density, high speed, low read power, and soft error rate (SER) immunity. The conductive lines 10 and 12 are used for writing data into the magnetic storage device 30. The MTJ stack 30 is located on the intersection of and between conventional conductive lines 10 and 12. Conventional conductive line 10 and line 12 are referred to as the conventional word line 10 and the conventional bit line 12, respectively. The names, however, are interchangeable. Other names, such as row line, column line, digit line, and data line, may also be used.
The conventional MTJ 30 stack primarily includes the free layer 38 with a changeable magnetic vector (not explicitly shown), the pinned layer 34 with a fixed magnetic vector (not explicitly shown), and an insulator 36 in between the two magnetic layers 34 and 38. The insulator 36 typically has a thickness that is low enough to allow tunneling of charge carriers between the magnetic layers 34 and 38. Layer 32 is usually a composite of seed layers and an antiferromagnetic (AFM) layer that is strongly coupled to the pinned magnetic layer. The AFM layer included in the layers 32 is usually Mn alloy, such as IrMn, NiMn, PdMn, PtMn, CrPtMn, and so on. The AFM layer is typically strongly exchanged coupled to the pinned layer 34 to ensure that the magnetic vector of the pinned layer 34 is strongly pinned in a particular direction.
When the magnetic vector of the free layer 38 is aligned with that of the pinned layer 34, the MTJ stack 30 is in a low resistance state. When the magnetic vector of the free layer 38 is antiparallel to that of the pinned layer 34, the MTJ stack 30 is in a high resistance state. Thus, the resistance of the MTJ stack 30 measured across the insulating layer 34 is lower when the magnetic vectors of the layers 34 and 38 are parallel than when the magnetic vectors of the layers 34 and 38 are in opposite directions.
Data is stored in the conventional MTJ stack 30 by applying a magnetic field to the conventional MTJ stack 30. The applied magnetic field has a direction chosen to move the changeable magnetic vector of the free layer 30 to a selected orientation. During writing, the electrical current I1 flowing in the conventional bit line 12 and I2 flowing in the conventional word line 10 yield two magnetic fields on the free layer 38. In response to the magnetic fields generated by the currents I1 and I2, the magnetic vector in free layer 38 is oriented in a particular, stable direction. This direction depends on the direction and amplitude of I1 and I2 and the properties and shape of the free layer 38. Generally, writing a zero (0) requires the direction of either I1 or I2 to be different than when writing a one (1). Typically, the aligned orientation can be designated a logic 1 or 0, while the misaligned orientation is the opposite, i.e., a logic 0 or 1, respectively.
Although the conventional MRAM 1 functions, one of ordinary skill in the art will readily recognize that the conventional MRAM 1 is subject to malfunctions. The field and, therefore, the current required to write to the conventional MTJ stack 30 depends upon the temperature of the conventional MRAM 1. In particular, the amplitude of the magnetic field required to switch the direction of the changeable magnetic vector in free layer 38 depends upon the temperature of the free layer 38. FIG. 1B depicts a graph 50 of the switching field for conventional MTJ stacks 30 versus temperature. Referring to FIGS. 1A and 1B, the data shown in the graph 50 are for two devices having different dimensions. As indicated in the graph 50, for a 0.25 μm by 0.5 μm device, the switching field can change from eighty Oersteds to sixty Oersteds when the temperature changes from zero degrees centigrade (two hundred seventh three K) to one hundred degrees centigrade (three hundred and seventy three K). The switching field is the field at which the magnetic vector of the free layer 38 changes direction (for example from antiparallel to the magnetic vector of the pinned layer 34 to parallel to the magnetic vector of the pinned layer 34, or vice versa). Similarly, the 0.9 μm by 1.8 μm device, the switching field increases between zero and one hundred degrees centigrade. Furthermore, by comparing the data for the 0.9 μm by 1.8 μm device with the data for the 0.25 μm by 0.5 μm device, it can be seen that the temperature dependency of switching field increases when the device size decreases. Consequently, the switching field of small devices is more strongly dependent upon temperature than the switching field of large devices. This change in the switching field with temperature can cause the conventional MRAM 1 to malfunction if the same write field is used at all temperatures. The malfunction(s) may include but are not limited to not being able to write data when temperature drops or accidentally writing data into unselected cells. This problem is expected to become much more significant as device size decreases.
Accordingly, what is needed is a method and system for providing a write field that compensates for temperature changes in the MRAM device. The present invention addresses such a need.